Design Verfication Engineer Job in Dabster Consulting Pvt. Ltd.

Design Verfication Engineer

London, ENG, GB, United Kingdom

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Job Description

Key Responsibilities:

Define and execute comprehensive verification plans based on design specifications and architecture. Develop and maintain UVM-based testbenches and environments. Write, simulate, and debug testcases using SystemVerilog. Perform block-level and subsystem-level verification, ensuring alignment with functional and performance targets. Run regression tests, analyse coverage reports, and identify design bugs. Collaborate with RTL designers, integration engineers, and system architects to ensure high-quality deliverables. Support gate-level simulations, formal verification, and other advanced verification methodologies.

Skills:

1. SOC Verification Experience on ARM Ecosystem

2. PCIE Experience and also PCIE-VIP usage experience

3. GLS working experience

4. Proficient in C/System Verilog and UVM

5. Working knowledge of GIT

6. Soft skill - Good Communication and willingness to learn

Job Type: Part-time

Pay: 80.00-90.00 per hour

Expected hours: 40 per week

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