Job Description

As the Principal Design Team Leader at AccelerComm, you will be working on 5G base stations on board satellites. This revolutionary technology is at the leading edge of satellite communications, and will underpin the next generation of mobile standards giving complete coverage to the globe. AccelerComm develop the base band signal processing technology, using hardware acceleration to generate world leading power efficiency. The Principal Design Team Lead will take a leading role in shaping the technical roadmap to extend the power efficiency for the latest generation space qualified devices, and then delivering this technology to our customers.

We are looking for a person with a proven track record of team leadership and delivering complex IP, who has a real interest in all aspects of the Intellectual Property development life cycle.

This is a hands-on role requiring exceptional team leadership skills alongside technical skills to drive the design, quality, and delivery of Layer 1 IP. This role will play a pivotal part in the growth of AccelerComm and our product portfolio.

Key Responsibilities

Provide strategic vision to inform technical decision-making and planning at a company level Take responsibility for the successful and timely delivery of projects by providing technical leadership Provide managerial leadership to build knowledge and support the team development Work closely with the exec team to translate product requirements into hardware team deliverables Support discussions with customers during presales and product development Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches Lead AccelerComm's engineering methodology, processes and design techniques Nurture professional growth of team members through regular mentoring, coaching, and feedback
Skills, Knowledge & Expertise

Essential Skills and Experience:

Track record of building and leading high performing collaborative teams Expert knowledge of an RTL design (Verilog, SystemVerilog) for complex ASIC/FPGA products A strong skillset in delivery of digital designs for ASIC and FPGA Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis Expert user of EDA tools for simulation and synthesis Knowledge and appreciation of project management methodologies across the design lifecycle including agile and waterfall, requirements capture and traceability.

Desirable:

Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming) Understanding of UVM verification techniques or practical experience using UVM for IP verification Experience using C++/SystemC for design modelling and integration Experience in Technology Readiness Models Experience in system architecture of a multi-disciplinary team project
Job Type: Full-time

Pay: 78,000.00-90,000.00 per year

Benefits:

Company pension Cycle to work scheme Free parking Life insurance On-site parking Private medical insurance
Work Location: Hybrid remote in Southampton SO16 7QJ