Job purpose
Here at Envisics, we are an internationally based innovator in the automotive industry specialising in the development and supply of holographic technologies to Tier 1s and OEMs, with or our primary focus currently on augmented reality ("AR") Head-up displays ("HUDs').
Here you will become vital part of our dedicated ASIC design team responsible for the full hologram calculation pipeline. Contribute to both control and data path design required for best performance and efficient resource utilisation.
We are looking for somebody that is versatile and experienced in RTL design Verilog and SV, preferably with ASIC experience. Acquired practical experience with IP, System/Sub-system and Top-level integration, taking part and numerous SoC projects, that include integrating embedded processor systems using ARM processor cores and ARM IPs.
Having been part of and actively taking part in and creating designs for complex systems/SoCs on different levels and areas.
Show a willingness to learn quicky on the job. Being methodical in approach to problem solving, analysis, design, implementation, and testing. Show willingness and drive to find the optimal solution and optimize for the best feasible implementation. Interact with HW-, SW- and R&D -teams. In this role you will be given a unique chance to nurse your creativity and bring innovative ideas to the table that will drive the development and quality of our HUD and the technology behind it.
Duties and responsibilities
Contribute to the overall SoC definition and implementation
Hologram processing pipeline component(s) design
System and Top-level integration
IP analysis and IP integration
Work closely with Systems engineers, Systems Architects, and processing core developers
Responsibility of tests and functional correctness of owned components/system parts
System performance analysis
Actively participate in code reviews and system design workshops
Evaluate, choose, and integrate 3rd party IPs for the design
Assemble and analyse functional and system requirements engineers, system architects and holographic research teams.
Use simulation tools and custom hardware to verify and validate components
Produce design, implementation, test(s) and analysis reports both for internal and external use
Assist in custom hardware design bring-up
Participate in and conduct ASIC post-silicon bring-up and chip validation
Qualifications
Essential:
Proficiency in Verilog and SV.
Experience with FPGA prototyping and functional simulation.
Integration and simulation of third-party IPs (e.g., memory controllers, CPUs).
SDC definition and timing closure.
Experience with standard buses (e.g., APB, AHB, AXI, Avalon, Wishbone) and interface protocols (e.g., SPI, QSPI, I2C, UART, DisplayPort, HDMI, DDR, MIPI).
Pinout definition and hands-on hardware debugging experience.
Hands-on experience of SoC design including integration of ARM based
control and processing sub-systems.
Memory system design and optimization
Timing closure and timing constraints definition
Scripting: Python, TCL, Matlab
Desirable:
Experience with ASIC design flow.
VHDL
Knowledge of linting and computer architecture/arithmetic.
Understanding of software architecture.
Programming C/C++, Embedded C, Assembler(ARM),
Good grasp of hardware schematics and PCB layout.
Experience with versioning systems, requirements capture-, integration- and change management- tools.
Control loop design
Experience with oscilloscopes, signal generators and other test tools
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