Job Description

Raspberry Pi Ltd

We design, license, and manufacture low-cost PCs, embedded systems, and microcontrollers, as well as accessories for these core products. Since 2012, we have sold over 40 million Raspberry Pi computers, with over seven million sold in 2020 alone. Together with the Raspberry Pi Foundation, we have made Raspberry Pi a trusted brand with hobbyists, educators, technical professionals, and - increasingly - consumers. Our current flagship product, Raspberry Pi 4, is a full-featured PC, priced from $35 and offering:

A quad-core, 64-bit Arm processor at 1.8GHz Between 2GB and 8GB of RAM Dual-monitor output Ultra HD media processing Wired and wireless networking

ASIC team

Raspberry Pi's ASIC team developed the first Raspberry Pi chip: the Raspberry Pi RP2040 microcontroller. This device was designed, verified, and implemented by our in-house team based in Cambridge, UK. The work of the ASIC team includes:

Architecture, tradeoffs with software/hardware RTL design IP selection and integration Verification at block and system level FPGA platforms for software development and extended verification Implementation including DFT, Synthesis, Place and Route, Timing closure and Signoff checks Package definition and working with assembly partners Validation and characterisation Test pattern generation and ATE bringup Production monitoring and management



We are looking to expand the team with some specific roles that we would like to fill. The roles are primarily located in Cambridge; however, we would consider remote working for the right candidate.

Requirements

DFT Engineer/Architect


Raspberry Pi is seeking a DFT specialist to join our innovative team. You would be involved in hands-on DFT implementation and verification across a variety of current silicon technologies. You would be responsible for design, development, and implementation of IC DFT test solutions, liaising across various groups and functions. You would be involved with architecture and development of test methodologies, ensuring adequate inclusion of test structures to enable fully and efficiently testable devices, including the following:

Hierarchical DFT (EDT flows) On-chip clocking structures ATPG compression, serialization, and multiplexing Guide scan insertion providing input to Synthesis scripts Review, assess, and correct DFT DRC warnings Create STA DFT mode constraints, review failing paths, create exception list for ATPG Simulation (behavioural and gate-level) RTL design of test structures BIST (Memory/Logic/IP)

Job requirements:

Willingness to contribute and share activities with a wider team Strong grounding in IC development flows Hands-on current experience with modern DFT tools Good understanding of partitioning and on-chip clocking Experience in ATPG and simulation debug



The following would also be useful:

Experience with either Cadence or Mentor DFT tools preferred Understanding of silicon technologies, finFET, and fault models Logic BIST implementation, full or as part of an ATPG flow * Familiarity with test access standards, e.g. IEEE1687